41 ms·
How did... how was that even possible?!
by LogicHoleFlaw 17y ago
How did... how was that even possible?!
- derobert 17y agoL1, L2, and L3 data cache make that easily possible. The write is cached, and the read is satisfied from the cache. Alternatively, there could be aliasing going on, and that read/write is actually going to a different DIMM (and thus corrupting memory elsewhere)
- anamax 17y agoNope. It wasn't caches, aliasing, or memory mapping. I could write to any physical address in the slots with no DIMMs and get back what I read, just like I could with the slots that had memory. I figured it out when I noticed that all reads (from the slots with no dimms), regardless of address, returned the last value written to any address. In other words, a read from 104 returned what I wrote to 100 if that was the last write. The data bus was behaving like a set of capacitors.