4 ms·

The x86 ISA has significant complexity to it. The essence of the problem is that the logic required to decode x86 instructions (originally designed to be featur

The x86 ISA has significant complexity to it. The essence of the problem is that the logic required to decode x86 instructions (originally designed to be featureful for assembly programmers' convenience) is large, compared to that required for the ARM ISA which was designed to be decoded in an efficient manner. That further logic certainly increases static power in terms of the extra area used, and also increases the dynamic power as more translation is required to get from an x86 instruction to the hardware control signals (I believe that the central part of the Atom effectively runs a different ISA translated from the x86 ISA via microcode).

tedunangst 17y ago
What percentage of an Atom is devoted to decode? Atom is around 45 million transistors. The PPro which also decoded to mini-RISC had 5 million. Somehow I don't think the Atom is really burning that much space/power on decode. You and gvb seem to imply that an ARM (RISC) chip which does less work per instruction somehow does more work per clock. I find that surprising. Otherwise, what is meant by the "emphasize raw clock rate" comment?
- sketerpot 17y ago
  The Cortex-A9 executes more instructions per clock because it can decode more than one instruction at a time (2 to 4, usually 4) and execute them out of order to get more instruction-level parallelism. Atom can decode a maximum of two instructions at a time, and executes them in order. The Atom also uses precious pipeline stages on decoding the x86 instruction set -- all of it. There are a lot of instructions there, and all but the most common require the processor to read sequences of several micro-instructions from a ROM. Now, the Atom tries to compensate for this with Hyperthreading: they share the decode unit among two threads (hypothetically) and have those threads share the execution units on the chip. This gives Atom a boost in performance per watt if you can find two processes that need to run at the same time. For single-threaded workloads, Cortex-A9 looks like it will continue to trounce Atom pretty severely, and for multi-threaded workloads, it's not expensive to put down some more A9 cores. It's not like they have to decode x86 instructions or anything, so they can be pretty darn small.

tedunangst 17y ago

What percentage of an Atom is devoted to decode? Atom is around 45 million transistors. The PPro which also decoded to mini-RISC had 5 million. Somehow I don't think the Atom is really burning that much space/power on decode. You and gvb seem to imply that an ARM (RISC) chip which does less work per instruction somehow does more work per clock. I find that surprising. Otherwise, what is meant by the "emphasize raw clock rate" comment?

sketerpot 17y ago
The Cortex-A9 executes more instructions per clock because it can decode more than one instruction at a time (2 to 4, usually 4) and execute them out of order to get more instruction-level parallelism. Atom can decode a maximum of two instructions at a time, and executes them in order. The Atom also uses precious pipeline stages on decoding the x86 instruction set -- all of it. There are a lot of instructions there, and all but the most common require the processor to read sequences of several micro-instructions from a ROM. Now, the Atom tries to compensate for this with Hyperthreading: they share the decode unit among two threads (hypothetically) and have those threads share the execution units on the chip. This gives Atom a boost in performance per watt if you can find two processes that need to run at the same time. For single-threaded workloads, Cortex-A9 looks like it will continue to trounce Atom pretty severely, and for multi-threaded workloads, it's not expensive to put down some more A9 cores. It's not like they have to decode x86 instructions or anything, so they can be pretty darn small.