The future might be in an FPGA fabric tightly coupled with generic RISC cores (things like Zynq SoCs, but with a tighter integration, allowing a direct access f

The future might be in an FPGA fabric tightly coupled with generic RISC cores (things like Zynq SoCs, but with a tighter integration, allowing a direct access from FPGA to the CPU internal registers, pipelines, etc.). Bigger macro cells (like entire ALUs, generic caches, etc.) might be useful too. This way hot spots can be optimised (even in a JIT engine in runtime) into hardware circuits. I played a bit with some crazy ideas like mixing HDLs with a low level C code (see the Mandelbrot example here: https://github.com/combinatorylogic/soc/tree/master/backends/small1/sw/long_hdltests https://github.com/combinatorylogic/soc/tree/master/backends... ) - this sort of things can become practical with a tighter integration between a CPU core and FPGA fabric (in my case it was a soft core, of course).