This can apply to x86, too. Not sure if all your users have TSX-capable CPUs? You're now shipping two binaries. Not sure if your users have AVX? Now you have at

This can apply to x86, too. Not sure if all your users have TSX-capable CPUs? You're now shipping two binaries. Not sure if your users have AVX? Now you have at least three binaries. Three code paths, not necessarily three binaries. It's easy enough to compile different variants of performance-critical routines and then select between them at run-time. I think ART takes the correct approach: ship IL and AOT it on the device. Hopefully some day we can get the same type of system for LLVM IR. This isn't necessarily optimal though. Having certain CPU features may make algorithmic changes useful -- e.g., switching between lookup tables and direct computation depending on whether you have the CPU features which make the direct computation fast. There's no way an AOT will be able to handle that for you.