2 ms·
It's pretty common for Verilog developers to think they're writing C code, but that's the first time I've heard the converse.
by CamperBob 17y ago
It's pretty common for Verilog developers to think they're writing C code, but that's the first time I've heard the converse.
- alttab 17y agoThe guy does some pretty interesting stuff - writes scripts to automatically generate structures so class variables are byte aligned and within cache lines and all that. But he has made some of the dumbest use of C++ I have ever seen. Verbs as classes, sometimes making it obvious that inheritance escapes him, and an entire cpp file over 10k lines long that does nothing but assert the mass amount of assumptions his code makes. The one method is literally called 'check_assumptions.' I'm not bitter though.