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It looks like they did something to opencl to get it to target FPGAs, and then went a level beyond and had some kind of high-powered memory interconnect between
by GFK_of_xmaspast 11y ago
It looks like they did something to opencl to get it to target FPGAs, and then went a level beyond and had some kind of high-powered memory interconnect between CPU and FPGA so that they can share memory space.
- varelse 11y agoAltera has developed an OpenCL->VHDL compiler. That said, GPU code does not directly map to VHDL code in an efficient manner. Note the utter absence of GPU vs FPGA OpenCL benchmarks in the wild and take the hint... https://www.altera.com/products/design-software/embedded-software-developers/opencl/overview.html https://www.altera.com/products/design-software/embedded-sof...
- p1esk 11y agoSo this is a physically separate CPU, not part of the FPGA chip, right? If so, what are the advantages compared to CPU implemented as a hard core in the FPGA?
- solarexplorer 11y agoThe separate CPU is much faster, because it has an entire die for itself and because it is a high-volume off-the-shelf chip. An embedded CPU/FPGA will suffer much more when it executes the serial part of the application on the embedded CPU. So if you remember Amdahls law... > What are the applications for this hybrid? Highly parallel applications with tight loops. These loops can be offloaded to the FPGA while the rest of the system can run as before. This approach allows you to use languages like FORTRAN/C/C++ without resorting to Verilog/VHDL, so it's much easier to adopt.
- p1esk 11y agoBut a separate die means bandwidth and latency of CPU-FPGA communication is greatly reduced. So if data has to be constantly moved between them, it might be a disadvantage. What are the applications for this hybrid?
- stonogo 11y agoThere is an entire chart devoted to this question in the article.