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This article is from May '15.
by pinewurst 11y ago
This article is from May '15.
- dang 11y agoYup, but we asked luu to repost it because it didn't get any attention the first time.
- p1esk 11y agoCan you give a brief summary of this product?
- dang 11y agoI can't! (I'm just a moderator and the guy who sent the repost invite.) But as a huge fan of all things Cray, I hope somebody knowledgeable will.
- GFK_of_xmaspast 11y agoIt looks like they did something to opencl to get it to target FPGAs, and then went a level beyond and had some kind of high-powered memory interconnect between CPU and FPGA so that they can share memory space.
- varelse 11y agoAltera has developed an OpenCL->VHDL compiler. That said, GPU code does not directly map to VHDL code in an efficient manner. Note the utter absence of GPU vs FPGA OpenCL benchmarks in the wild and take the hint... https://www.altera.com/products/design-software/embedded-software-developers/opencl/overview.html https://www.altera.com/products/design-software/embedded-sof...
- p1esk 11y agoSo this is a physically separate CPU, not part of the FPGA chip, right? If so, what are the advantages compared to CPU implemented as a hard core in the FPGA?
- solarexplorer 11y agoThe separate CPU is much faster, because it has an entire die for itself and because it is a high-volume off-the-shelf chip. An embedded CPU/FPGA will suffer much more when it executes the serial part of the application on the embedded CPU. So if you remember Amdahls law... > What are the applications for this hybrid? Highly parallel applications with tight loops. These loops can be offloaded to the FPGA while the rest of the system can run as before. This approach allows you to use languages like FORTRAN/C/C++ without resorting to Verilog/VHDL, so it's much easier to adopt.
- p1esk 11y agoBut a separate die means bandwidth and latency of CPU-FPGA communication is greatly reduced. So if data has to be constantly moved between them, it might be a disadvantage. What are the applications for this hybrid?
- stonogo 11y agoThere is an entire chart devoted to this question in the article.
- solarexplorer 11y agoIf I understand correctly they combine a standard X86 processor with two FPGAs. One FPGA runs a custom CPU called MAP and the other manages the communication between the two CPUs, memory and other boards/peripherals. The develoment system accepts standard C/C++ code and emits two programs: one for the X86 processor, one for the MAP processor and a hardware description to adapt the MAP processor to the specific requirements of the source program. For some programs this can be a big win (and for others not so much).