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Note this is the same Clifford Wolf who has built a Verilog synthesizer [1] and reverse engineered the Lattice FPGA bitstream format [2]. On a slightly differe
by pdq 11y ago
Note this is the same Clifford Wolf who has built a Verilog synthesizer [1] and reverse engineered the Lattice FPGA bitstream format [2].
On a slightly different topic, the RISC-V group has built an impressive Javascript RISC-V emulator that boots Linux in your browser: http://riscv.org/angel/ http://riscv.org/angel/
[1] https://github.com/cliffordwolf/yosys https://github.com/cliffordwolf/yosys
[2] http://www.clifford.at/icestorm/ http://www.clifford.at/icestorm/
- tkinom 11y agoVery nice! Boot http://riscv.org/angel/ http://riscv.org/angel/ into linux busybox in the browser / # cat /proc/cpuinfo CPU info: PUNT! / # What does "PUNT!" mean?
- monocasa 11y agoIt means that there's still work to do on the Linux port and RISC-Vs supervisor mode ISA in general.
- duskwuff 11y agoIt means that the RISC-V Linux port hasn't decided what to put in /proc/cpuinfo yet. The contents of that file are not standardized across architectures, and indeed there isn't much meaningful information to provide there on certain CPUs.
- ant6n 11y agoThere's an OpenRisc in-browser emulator which seems to give you a more functional linux: http://s-macke.github.io/jor1k http://s-macke.github.io/jor1k The cpu in /proc/cpuinfo is OpenRISC-12 @ 20MHz ;)