A recent HN discussion referenced a paper that analyzed architectures in terms of ... addressing modes, as I recall. The thesis as I recall was something like,

A recent HN discussion referenced a paper that analyzed architectures in terms of ... addressing modes, as I recall. The thesis as I recall was something like, the more difficult or delayed it was to pre-fetch data, the harder it was to make it fast, and the rank ordered ISAs were a good match what I recalled happened in the market. E.g. the VAX ISA was quite bad, and DEC indeed really struggled to make it fast, and didn't bother trying to make a 64 bit version of it. If you're primarily comparing the two major survivors of this battle, as the interesting paper you linked to does, less competitive ISAs that didn't make the cut would already be removed from serious consideration. Heck, the great success of both the Intel and ARM ISAs was largely a matter of historical accident than intended design, e.g. the 8086 was designed to be compatible with earlier 8 bit designs and to fit in a 20,000 active gate budget. As I've described elsewhere, the ARM was designed to hit a power dissipation target (which it did by a huge margin), and since then the compact Thumb ISAs have been added to it.