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Indeed. The rise and fall of RISC designs coincides with a period where CPU and memory speeds were much better matched, and there was an extreme premium on the
by hga 11y ago
Indeed. The rise and fall of RISC designs coincides with a period where CPU and memory speeds were much better matched, and there was an extreme premium on the number of gates consumed by your design, to fit it all in a single economically manufacturable (i.e. small) silicon die.
I say "fall" because ARM had an additional advantage, the market which they were targeting couldn't afford ceramic packages, only plastic, and they didn't have the simulation capability to confirm their 2nd design would hit their power dissipation target (they were in fact using chips from their 1st design), so they were very conservative and hit their target with a very large margin to spare, maybe a factor 10?
So with that extra advantage, and a good business model (better than any competitor at the critical times? Certainly MIPS), they got more and more design wins where power was a consideration. In 2001 at Lucent I worked on a power constrained monster board that provisioned something like 300 modem lines, it had specialized ADI chips to do the heavy lifting, they were controlled by a bunch of ARM chips, and it had one housekeeping MIPS chip that was standard for these boards. And they pretty much own the mobile market that isn't tied to x86 by an existing software base, or that needs more horsepower than they're currently offering.
- danellis 11y agoI remember Steve Furber told us in CS that the first time he tested the original ARM they got back from the fab, they forgot to connect the power lines. It worked anyway, just from the power on the I/O lines.
- hga 11y agoHah! No need to meter the power used to know they'd achieved their goal by a large margin. I found the interview of him I was making my comments from, here's the critical 2 paragraphs (http://queue.acm.org/detail.cfm?id=1716385 http://queue.acm.org/detail.cfm?id=1716385): SF The ARM was conceived as a processor for a tethered desktop computer, where ultimate low power was not a requirement. We wanted to keep it low cost, however, and at that time, keeping the chip low cost meant ensuring it would go in low-cost packaging, which meant plastic. In order to use plastic packaging, we had to keep the power dissipation below a watt—that was a hard limit. Anything above a watt would make the plastic packaging unsuitable, and the package would cost more than the chip itself. We didn't have particularly good or dependable power-analysis tools in those days; they were all a bit approximate. We applied Victorian engineering margins, and in designing to ensure it came out under a watt, we missed, and it came out under a tenth of a watt—really low power.
- pkaye 11y agoIt happens due to ESD protection diodes on the I/O lines. You can still see this happen in some of the current low power microcontrollers.
- userbinator 11y agoAlso, RISC began at a time when main memory was actually slightly faster than the CPU[1], and the bottleneck for the contemporary CISCs was instruction decoding. With memory bandwidth to spare, it made a lot of sense to simplify the decoders to make them faster, resulting in sparser encodings which used more storage and bandwidth. Had memory always been slower, perhaps things would've turned out very differently - multicycle decoders and more complex instruction sets might've become far more common, and less caching. [1] If I remember correctly, I saw the graph showing this memory-faster-than-CPU in the famous Hennessy&Patterson book, which is somewhat ironic since it quite heavily preaches about the virtues of MIPS.