4 ms·

https://research.cs.wisc.edu/vertical/papers/2013/isa-power-struggles-tr.pdf https://research.cs.wisc.edu/vertical/papers/2013/isa-power-... Generally, the tho

by yifanlu 11y ago

https://research.cs.wisc.edu/vertical/papers/2013/isa-power-struggles-tr.pdf https://research.cs.wisc.edu/vertical/papers/2013/isa-power-... Generally, the thought is that ISA doesn't really affect performance.

joosters 11y ago
Interesting paper, thanks for linking it in here. I don't really understand their conclusions though. They show that the behaviour of x86 (converted to uOps) and ARM is similar (instructions in flight, etc), but I can't see how their the end result (the i7 is vastly faster, sometimes 25x faster than the ARM A8/A9) can demonstrate that the ARM instruction set is not responsible for some of the performance difference. The paper certainly demonstrates that there is no performance hit going the other way, i.e. the extra complexity of the x86 instruction is never a bottleneck, and once translated to uOps, the instructions are broadly comparable to RISC. I get that, but I don't get how they can also conclude that the ARM ISA is not a performance limiter. They don't investigate code size or memory/cache performance, for instance.
- userbinator 11y ago
  Also, synthetically scaling an i7 down to 1GHz, assuming the performance will be proportional, is not very fair - because of how much faster its core runs compared to memory, (contrast this with the ARMs which are closer) with decreasing core speed the performance decrease will be sublinear, whereas power consumption is more like exponential in frequency: http://i.stack.imgur.com/daciI.png http://i.stack.imgur.com/daciI.png I'd expect actually running an i7 at 1GHz vs 3GHz to be far more power efficient than their scaling indicates. There's some past HN discussion about that paper/an article related to it here: https://news.ycombinator.com/item?id=8235120 https://news.ycombinator.com/item?id=8235120
hga 11y ago
A recent HN discussion referenced a paper that analyzed architectures in terms of ... addressing modes, as I recall. The thesis as I recall was something like, the more difficult or delayed it was to pre-fetch data, the harder it was to make it fast, and the rank ordered ISAs were a good match what I recalled happened in the market. E.g. the VAX ISA was quite bad, and DEC indeed really struggled to make it fast, and didn't bother trying to make a 64 bit version of it. If you're primarily comparing the two major survivors of this battle, as the interesting paper you linked to does, less competitive ISAs that didn't make the cut would already be removed from serious consideration. Heck, the great success of both the Intel and ARM ISAs was largely a matter of historical accident than intended design, e.g. the 8086 was designed to be compatible with earlier 8 bit designs and to fit in a 20,000 active gate budget. As I've described elsewhere, the ARM was designed to hit a power dissipation target (which it did by a huge margin), and since then the compact Thumb ISAs have been added to it.
- rdc12 11y ago
  Do you have a link to that discussion/paper, sounds intersting
  - hga 11y ago
    Sorry, I haven't been able to find it.

by yifanlu 11y ago

joosters 11y ago

Interesting paper, thanks for linking it in here. I don't really understand their conclusions though. They show that the behaviour of x86 (converted to uOps) and ARM is similar (instructions in flight, etc), but I can't see how their the end result (the i7 is vastly faster, sometimes 25x faster than the ARM A8/A9) can demonstrate that the ARM instruction set is not responsible for some of the performance difference. The paper certainly demonstrates that there is no performance hit going the other way, i.e. the extra complexity of the x86 instruction is never a bottleneck, and once translated to uOps, the instructions are broadly comparable to RISC. I get that, but I don't get how they can also conclude that the ARM ISA is not a performance limiter. They don't investigate code size or memory/cache performance, for instance.

userbinator 11y ago
Also, synthetically scaling an i7 down to 1GHz, assuming the performance will be proportional, is not very fair - because of how much faster its core runs compared to memory, (contrast this with the ARMs which are closer) with decreasing core speed the performance decrease will be sublinear, whereas power consumption is more like exponential in frequency: http://i.stack.imgur.com/daciI.png http://i.stack.imgur.com/daciI.png I'd expect actually running an i7 at 1GHz vs 3GHz to be far more power efficient than their scaling indicates. There's some past HN discussion about that paper/an article related to it here: https://news.ycombinator.com/item?id=8235120 https://news.ycombinator.com/item?id=8235120

hga 11y ago

A recent HN discussion referenced a paper that analyzed architectures in terms of ... addressing modes, as I recall. The thesis as I recall was something like, the more difficult or delayed it was to pre-fetch data, the harder it was to make it fast, and the rank ordered ISAs were a good match what I recalled happened in the market. E.g. the VAX ISA was quite bad, and DEC indeed really struggled to make it fast, and didn't bother trying to make a 64 bit version of it. If you're primarily comparing the two major survivors of this battle, as the interesting paper you linked to does, less competitive ISAs that didn't make the cut would already be removed from serious consideration. Heck, the great success of both the Intel and ARM ISAs was largely a matter of historical accident than intended design, e.g. the 8086 was designed to be compatible with earlier 8 bit designs and to fit in a 20,000 active gate budget. As I've described elsewhere, the ARM was designed to hit a power dissipation target (which it did by a huge margin), and since then the compact Thumb ISAs have been added to it.

rdc12 11y ago
Do you have a link to that discussion/paper, sounds intersting
- hga 11y ago
  Sorry, I haven't been able to find it.