5 ms·

I had wondered this myself -- it seems reasonable to see limiting the precision of activation as a form of regularization, as the author alludes to. For me, th

I had wondered this myself -- it seems reasonable to see limiting the precision of activation as a form of regularization, as the author alludes to. For me, the place we'll eventually end up is obviously custom deep learning / evaluation chips that perform analogue operations using transistors in their linear regime (like how op-amps work). These chips would be programmed merely to express the tensor operation graph, essentially analogue tensor FPGAs. This should bring multiple order-of-magnitude reductions in power consumption and increases in evaluation speed. And when you don't have a clock there might also be interesting ways of dealing with time in which you don't discretize and unroll, like one currently does with GRUs or LSTMs.

fchollet 11y ago
Let the laws of physics do the recurrent math for you. Analog RNN computers would be very interesting, but they would first setting in stone the basics of the algorithms we use. We are still only beginning to explore the algorithm space, and this requires a flexibility that analog computers (or even ASICs or FPGAs) don't provide. It's still not clear whether the future of AI will even involve neural networks at all. Intuitively, they seem so inefficient.
darkmighty 11y ago
I agree that this kind of naive analog computing sounds very attractive with those simple linear operations (linear networks have been exhaustively studied, as you noted you essentially need only resistors and amplifiers). But it's not entirely obvious to me they ought to be better than digital electronics for comparable precision (considering their noise) and power consumption. I think you may get into trouble in the small current regime due to quantum mechanics: while you can do digital electronics with only a few electrons, you may need a large number to be able to maintain good linearity. An then there's the fact you can deal with exponentially larger numbers with roughly linearly (or polynomial) increasing memory, while if you use analog circuits you have to pay a quadratic cost on the exponential, so ~n^k vs ~exp(2n) power consumption doesn't look good from this pov. But who knows, as the article points out the nonlinearities of the network may miraculously make it work even with very poor linearity and poor precision. It remains to be tested.
- taliesinb 11y ago
  > n then there's the fact you can deal with exponentially larger numbers with roughly linearly (or polynomial) increasing memory, while if you use analog circuits you have to pay a quadratic cost on the exponential, so ~n^k vs ~exp(2n) power consumption doesn't look good from this pov. That's true, I feel stupid for not having thought of that! I'm not an electrical engineer, but with the FETs that modern Intel chips are using, what fraction of their power consumption comes from parasitic gate capacitance, versus other losses? And if you operated in the linear region, what's the ballpark steady-state I_SD current you'd need on one FET to drive the gate of the next FET? I think that's what this comes down to: if gate capacitance dominates other losses even in the linear regime, you still win by not having a clock and lots of digital transitions. You could even imagine exploiting that: apply 'slow' augmentations of the input data that get you the equivalent of a bunch of iterations on a single example batch, while incurring a much smaller fraction of that initial cost because activations aren't going to change nearly as much as switching to a whole new example batch.
  - p1esk 11y ago
    "parasitic gate capacitance" - not sure if you want to call it "parasitic", after all, a gate capacitance is what makes everything work! Power is mainly lost via leakage (the smaller the transistor, the more it leaks), and via interconnect capacitance, which dominates all other capacitances in modern circuits.
    - taliesinb 11y ago
      > "parasitic gate capacitance" - not sure if you want to call it "parasitic", after all, a gate capacitance is what makes everything work! Of course, but the 'ideal' FET has zero gate capacitance, despite that being the way they work. > Power is mainly lost via leakage (the smaller the transistor, the more it leaks), and via interconnect capacitance, which dominates all other capacitances in modern circuits. Interconnect meaning things like the buses? There's no reason to want a von Neumann architecture for an analog chip. If that leaves leakage, I suppose an analog chip would be the beneficiary of needing a lot fewer transistors per op.
rndn 11y ago
What are your thoughts on using memristors for neural networks? They appear to have pretty good properties for that.
- taliesinb 11y ago
  "Training and Operation of an Integrated Neuromorphic Network Based on Metal-Oxide Memristors", which appeared in Nature recently: http://arxiv.org/ftp/arxiv/papers/1412/1412.0611.pdf http://arxiv.org/ftp/arxiv/papers/1412/1412.0611.pdf
nightski 11y ago
Wouldn't noise be a huge issue?
- taliesinb 11y ago
  Deep nets love noise, because with so many parameters they are very vulnerable to overfitting. For example, dropout, which is almost ubiquitous for deep learning, basically makes activations 'wrong' 50% of the time during training.
  - p1esk 11y ago
    That's not true. NNs don't like noise, there have been a lot of research done about effect of noise on NNs in the 90s. Random noise over a certain threshold will progressively degrade the performance of NNs, and below the threshold will have no effect. Dropout is not the same as random noise. By using dropout you eliminate some neurons from making contribution. As a result, you effectively train many smaller nets, each one adjusting its available weights to perform the same task. During testing, there's no noise - all neurons are back in business and contributing.
    - srean 11y ago
      I am pretty sure that parent meant DNNs love to fit noise. So you two are in strong agreement.
      - p1esk 11y ago
        No, we are talking about a random electrical circuit noise in the analog NN hardware. Of course, if the noise is known and fixed, the net could learn to compensate (to a certain extent). The noise we are talking about is like when you put your finger on the chip, and raise its temperature by 10 degrees, the whole thing needs to be retrained.
        taliesinb 11y ago
        > The noise we are talking about is like when you put your finger on the chip, and raise its temperature by 10 degrees, the whole thing needs to be retrained. What would change with temperature that would require retraining? Are you saying the output of an op could depend sensitively on temperature, or that higher temperatures would increase things like thermal or shot noise? Why would the latter require retraining?

fchollet 11y ago

Let the laws of physics do the recurrent math for you. Analog RNN computers would be very interesting, but they would first setting in stone the basics of the algorithms we use. We are still only beginning to explore the algorithm space, and this requires a flexibility that analog computers (or even ASICs or FPGAs) don't provide. It's still not clear whether the future of AI will even involve neural networks at all. Intuitively, they seem so inefficient.

darkmighty 11y ago

I agree that this kind of naive analog computing sounds very attractive with those simple linear operations (linear networks have been exhaustively studied, as you noted you essentially need only resistors and amplifiers). But it's not entirely obvious to me they ought to be better than digital electronics for comparable precision (considering their noise) and power consumption. I think you may get into trouble in the small current regime due to quantum mechanics: while you can do digital electronics with only a few electrons, you may need a large number to be able to maintain good linearity. An then there's the fact you can deal with exponentially larger numbers with roughly linearly (or polynomial) increasing memory, while if you use analog circuits you have to pay a quadratic cost on the exponential, so ~n^k vs ~exp(2n) power consumption doesn't look good from this pov. But who knows, as the article points out the nonlinearities of the network may miraculously make it work even with very poor linearity and poor precision. It remains to be tested.

taliesinb 11y ago
> n then there's the fact you can deal with exponentially larger numbers with roughly linearly (or polynomial) increasing memory, while if you use analog circuits you have to pay a quadratic cost on the exponential, so ~n^k vs ~exp(2n) power consumption doesn't look good from this pov. That's true, I feel stupid for not having thought of that! I'm not an electrical engineer, but with the FETs that modern Intel chips are using, what fraction of their power consumption comes from parasitic gate capacitance, versus other losses? And if you operated in the linear region, what's the ballpark steady-state I_SD current you'd need on one FET to drive the gate of the next FET? I think that's what this comes down to: if gate capacitance dominates other losses even in the linear regime, you still win by not having a clock and lots of digital transitions. You could even imagine exploiting that: apply 'slow' augmentations of the input data that get you the equivalent of a bunch of iterations on a single example batch, while incurring a much smaller fraction of that initial cost because activations aren't going to change nearly as much as switching to a whole new example batch.
- p1esk 11y ago
  "parasitic gate capacitance" - not sure if you want to call it "parasitic", after all, a gate capacitance is what makes everything work! Power is mainly lost via leakage (the smaller the transistor, the more it leaks), and via interconnect capacitance, which dominates all other capacitances in modern circuits.
  - taliesinb 11y ago
    > "parasitic gate capacitance" - not sure if you want to call it "parasitic", after all, a gate capacitance is what makes everything work! Of course, but the 'ideal' FET has zero gate capacitance, despite that being the way they work. > Power is mainly lost via leakage (the smaller the transistor, the more it leaks), and via interconnect capacitance, which dominates all other capacitances in modern circuits. Interconnect meaning things like the buses? There's no reason to want a von Neumann architecture for an analog chip. If that leaves leakage, I suppose an analog chip would be the beneficiary of needing a lot fewer transistors per op.

rndn 11y ago

What are your thoughts on using memristors for neural networks? They appear to have pretty good properties for that.

taliesinb 11y ago
"Training and Operation of an Integrated Neuromorphic Network Based on Metal-Oxide Memristors", which appeared in Nature recently: http://arxiv.org/ftp/arxiv/papers/1412/1412.0611.pdf http://arxiv.org/ftp/arxiv/papers/1412/1412.0611.pdf

nightski 11y ago

Wouldn't noise be a huge issue?

taliesinb 11y ago
Deep nets love noise, because with so many parameters they are very vulnerable to overfitting. For example, dropout, which is almost ubiquitous for deep learning, basically makes activations 'wrong' 50% of the time during training.
- p1esk 11y ago
  That's not true. NNs don't like noise, there have been a lot of research done about effect of noise on NNs in the 90s. Random noise over a certain threshold will progressively degrade the performance of NNs, and below the threshold will have no effect. Dropout is not the same as random noise. By using dropout you eliminate some neurons from making contribution. As a result, you effectively train many smaller nets, each one adjusting its available weights to perform the same task. During testing, there's no noise - all neurons are back in business and contributing.
  - srean 11y ago
    I am pretty sure that parent meant DNNs love to fit noise. So you two are in strong agreement.
    - p1esk 11y ago
      No, we are talking about a random electrical circuit noise in the analog NN hardware. Of course, if the noise is known and fixed, the net could learn to compensate (to a certain extent). The noise we are talking about is like when you put your finger on the chip, and raise its temperature by 10 degrees, the whole thing needs to be retrained.
      - taliesinb 11y ago
        > The noise we are talking about is like when you put your finger on the chip, and raise its temperature by 10 degrees, the whole thing needs to be retrained. What would change with temperature that would require retraining? Are you saying the output of an op could depend sensitively on temperature, or that higher temperatures would increase things like thermal or shot noise? Why would the latter require retraining?