3 ms·
Verilog which is loosely based on C also blindly followed this trend, but created a big mess. In Verilog you can say: module foo(a); parameter width =
by jhallenworld 11y ago
Verilog which is loosely based on C also blindly followed this trend, but created a big mess.
In Verilog you can say:
module foo(a);
parameter width = 20;
input [width-1:0] a;
But "ANSI" Verilog is "improved":
module foo(input [19:0] a);
Oops.. no place to put the parameter.. so later on they amended:
module #(parameter width=20) foo(input [width-1:0] a);
They should have just removed the argument list:
module foo;
input a;
This would have worked for C as well:
int foo()
int a, b, c;
{