3 ms·

Well, IA64 is not just in-order, but Very Long Instruction Word (VLIW), per Wikipedia a 128 bit instruction had 3 instructions. If your compiler is not smart e

by hga 11y ago

Well, IA64 is not just in-order, but Very Long Instruction Word (VLIW), per Wikipedia a 128 bit instruction had 3 instructions. If your compiler is not smart enough (hmmm, especially if your language is too low level, like C/C++), it sure looks like "just in time" out-of-ordering will beat VLIW in keeping your execution engines running. And surely caching makes a big difference here. I don't know how to compare a MIPS family in-order superscalar with Intel's P6 style out-of-order. ARM out-of-order cores are supposed to be quite a bit faster than their in-order designs in IRL, aren't they?

sliken 11y ago
Most in order architectures approximately double their performance per clock whe they switch to out-of-order. Examples include cortex-a57 vs a53. Alpha 21264 vs alpha 21164. As well as many of the atoms until very recently vs core2 and similar chips. With the various arm derivatives from qualcomm, samsung, and apple a under 2 GHz in order CPU doesn't sound particularly impressive. Especially when they talk about "under 30 watts", that's intel territory, not tablets let alone smart phones. Trying to emulate arm and beat arm on price/perf or perf/watt seems like a long shot with an in-order mips64. Similarly beating intel at price/perf or perf/watt seems exceedingly unlikely with lower IPC and a MUCH slower clock. The only thing that makes these mips64 look good is the even slower previous generation mips.
- alexvoica 11y ago
  I agree on the out-of-/in-order commentary. But to paraphrase, with great performance comes great power consumption. http://www.anandtech.com/show/9330/exynos-7420-deep-dive/5 http://www.anandtech.com/show/9330/exynos-7420-deep-dive/5 I perceive the situation on binary translation in a slightly different way. I think the aim here is to perhaps ensure that some legacy code written for x86/ARM also runs alongside the apps written for MIPS. So they are not trying to compete, but ensure they have a broad(er) ecosystem.
  - hga 11y ago
    with great performance comes great power consumption Heh. And I suppose that's intrinsically true, with the added shadow registers and logic to drive it all?

by hga 11y ago

sliken 11y ago

Most in order architectures approximately double their performance per clock whe they switch to out-of-order. Examples include cortex-a57 vs a53. Alpha 21264 vs alpha 21164. As well as many of the atoms until very recently vs core2 and similar chips. With the various arm derivatives from qualcomm, samsung, and apple a under 2 GHz in order CPU doesn't sound particularly impressive. Especially when they talk about "under 30 watts", that's intel territory, not tablets let alone smart phones. Trying to emulate arm and beat arm on price/perf or perf/watt seems like a long shot with an in-order mips64. Similarly beating intel at price/perf or perf/watt seems exceedingly unlikely with lower IPC and a MUCH slower clock. The only thing that makes these mips64 look good is the even slower previous generation mips.

alexvoica 11y ago
I agree on the out-of-/in-order commentary. But to paraphrase, with great performance comes great power consumption. http://www.anandtech.com/show/9330/exynos-7420-deep-dive/5 http://www.anandtech.com/show/9330/exynos-7420-deep-dive/5 I perceive the situation on binary translation in a slightly different way. I think the aim here is to perhaps ensure that some legacy code written for x86/ARM also runs alongside the apps written for MIPS. So they are not trying to compete, but ensure they have a broad(er) ecosystem.
- hga 11y ago
  with great performance comes great power consumption Heh. And I suppose that's intrinsically true, with the added shadow registers and logic to drive it all?