5 ms·

Uh? That's quite different AFAIK: two CPU cores doesn't share their registers, those disjoint streams do.

• Someone 11y ago
  I know this architecture tries to innovate everywhere, but disjoint streams that share registers, but not caches? I haven't read all documentation on the Mill, but I would expect that that sharing part means that both streams can read or one can write each register.
  • willvarfar 11y ago
    (Mill team) The Mill is Havard architecture. Each Mill core has two separate physically separated instruction caches that each feed a dedicated decoder, which decodes for a distinct set of pipelines.
    • renox 11y ago
      > which decodes for a distinct set of pipelines I apologize for my mistake, I hope that it hasn't induced too many confusions (I take it that 'distinct set of pipelines' means distinct operation and 'belt' so the registers aren't shared).
      • willvarfar 11y ago
        No need to apologise :) The pipelines are distinct, but the set of ops that any particular pipeline supports is arbitrary (as in picked by the HW guys who have to fit the FUs in) and the belt is shared. The belt is where the two sides join. We tend to get good entropy putting the flow on one side and exec on the other, and that's nice for humans to model too, but there is no technical requirement. The thing about the Mill is its easily customisable. If you have some new FU (lets say you want a particular op that assists in say encrpytion) you can choose where you put it, and how many pipelines you put it in etc.
        • renox 11y ago
          Especially since if the belt is shared then in fact I remembered correctly the presentation.