6 ms·

The Mill CPU is going on and on as going to be awesome some day. I spoke with one their guys at Greg Chesson's wake, it seemed open ended. Yup, you have good

The Mill CPU is going on and on as going to be awesome some day. I spoke with one their guys at Greg Chesson's wake, it seemed open ended. Yup, you have good ideas. How about you ship? Then we can see if the ideas meet reality and work. I'm friends with one the guys who did the P6. Which became the basis for pretty much any x86 chip. He shipped stuff. Ideas are easy, execution is hard, I have yet to see the Mill people execute. I'd be crazy happy if they stepped up and made me look stupid because they shipped a kick ass chip.

javajosh 11y ago
I know right? Even a crappy CPU based on the Mill concept would be good. You could at least perform computational efficiency (ops/watt) style benchmarks. I'm sort of curious what the endgame is, myself.
uxcn 11y ago
As I understand, they aren't seeking venture capital backing, so progress is slow. I know they have (had) plans to implement a Mill on an FPGA, but even going to a usable ASIC will probably be a challenge. It's a major architectural change as well. Most existing systems rely on virtual memory, which the Mill doesn't support.
- adwn 11y ago
  > Most existing systems rely on virtual memory, which the Mill doesn't support. I believe you're mistaken. The Mill does support virtual memory; the main differences to most systems are that its caches use virtual addresses (the TLB is between the L2 cache and the DRAM), and that it's a single-address-space architecture.
  - uxcn 11y ago
    Sorry, I did misunderstand. I see. I was under the impression they were entirely doing away with the hardware necessary for virtual memory.
  - aidenn0 11y ago
    ARM did that with L1 cache in the '90s and it was terrible for targeting a VM OS to. Cache aliasing is a nightmare and a never-ending source of bugs for e.g. shared memory.
    - vanderZwan 11y ago
      Maybe this talk answers questions you may have? (since it's specifically about memory on the Mill CPU) http://millcomputing.com/docs/memory/ http://millcomputing.com/docs/memory/
    - mike_hearn 11y ago
      It's very likely that they will need to write their own OS from scratch for the Mill. They might be able to reuse a lot of code from Linux, but it won't be Linux, as the whole ethos of the Mill is to rethink everything. In particular the Mill does not have the same notion of a process, the CPU itself is aware of threading, it has its own security design that isn't anything like user/supervisor mode, there are no syscalls, and programs have to be specialised before they can be run, a la ART on Android. I suspect once they have LLVM up and running, one of the next biggest wins they'll want to go for is porting HotSpot. The only other company I'm aware of that was able to actually make money selling a really crazy custom CPU architecture is Azul with their Vega arch, and they did it by making Java bytecode their exposed bytecode. The actual CPU opcodes were an implementation detail and everything compiled on the fly. The nice thing about porting the JVM is tons of business-critical, performance sensitive code would Just Work™. And then you have a ready made market for companies with huge Java (e.g. Hadoop) jobs that are very power/performance tradeoff sensitive.
      - dogma1138 11y ago
        Is VEGA an actual discrete CPU architecture or something they've licensed/copied from existing chips? Azul made their money from selling high performance JVM's they have their "VEGA" compute appliances for Java applications but I've never actually seen their ISA documentation for the hardware which would be a very interesting thing to see....

javajosh 11y ago

I know right? Even a crappy CPU based on the Mill concept would be good. You could at least perform computational efficiency (ops/watt) style benchmarks. I'm sort of curious what the endgame is, myself.

uxcn 11y ago

As I understand, they aren't seeking venture capital backing, so progress is slow. I know they have (had) plans to implement a Mill on an FPGA, but even going to a usable ASIC will probably be a challenge. It's a major architectural change as well. Most existing systems rely on virtual memory, which the Mill doesn't support.

adwn 11y ago
> Most existing systems rely on virtual memory, which the Mill doesn't support. I believe you're mistaken. The Mill does support virtual memory; the main differences to most systems are that its caches use virtual addresses (the TLB is between the L2 cache and the DRAM), and that it's a single-address-space architecture.
- uxcn 11y ago
  Sorry, I did misunderstand. I see. I was under the impression they were entirely doing away with the hardware necessary for virtual memory.
- aidenn0 11y ago
  ARM did that with L1 cache in the '90s and it was terrible for targeting a VM OS to. Cache aliasing is a nightmare and a never-ending source of bugs for e.g. shared memory.
  - vanderZwan 11y ago
    Maybe this talk answers questions you may have? (since it's specifically about memory on the Mill CPU) http://millcomputing.com/docs/memory/ http://millcomputing.com/docs/memory/
  - mike_hearn 11y ago
    It's very likely that they will need to write their own OS from scratch for the Mill. They might be able to reuse a lot of code from Linux, but it won't be Linux, as the whole ethos of the Mill is to rethink everything. In particular the Mill does not have the same notion of a process, the CPU itself is aware of threading, it has its own security design that isn't anything like user/supervisor mode, there are no syscalls, and programs have to be specialised before they can be run, a la ART on Android. I suspect once they have LLVM up and running, one of the next biggest wins they'll want to go for is porting HotSpot. The only other company I'm aware of that was able to actually make money selling a really crazy custom CPU architecture is Azul with their Vega arch, and they did it by making Java bytecode their exposed bytecode. The actual CPU opcodes were an implementation detail and everything compiled on the fly. The nice thing about porting the JVM is tons of business-critical, performance sensitive code would Just Work™. And then you have a ready made market for companies with huge Java (e.g. Hadoop) jobs that are very power/performance tradeoff sensitive.
    - dogma1138 11y ago
      Is VEGA an actual discrete CPU architecture or something they've licensed/copied from existing chips? Azul made their money from selling high performance JVM's they have their "VEGA" compute appliances for Java applications but I've never actually seen their ISA documentation for the hardware which would be a very interesting thing to see....