I was responding mainly to the assertion about the trivial amount of extra circuitry required. The cacheline-crossing case means that it's a more complicated a

I was responding mainly to the assertion about the trivial amount of extra circuitry required. The cacheline-crossing case means that it's a more complicated affair than just shuffling some bytes around as in the within-cacheline case. The "accesses across cachelines require LOCK to be atomic" x86 case is also illustrative - for example should the pthreads implementation include the LOCK prefix just in case you have embedded your pthread_mutex_t in a packed structure where it ends up unaligned?