You are correct, mainstream CPUs load in cache line quanta. They can't do anything smaller. If your value straddles a cache line boundary then you load two li

You are correct, mainstream CPUs load in cache line quanta. They can't do anything smaller. If your value straddles a cache line boundary then you load two lines. That's why cache-aligned values are sometimes critical to performance of certain codes. Intel will soon be marketing CPUs with 512-bit registers. At that time the register width and the cache line width will be the same. That will be novel.