3 ms·
This is a great post, and really enhances my otherwise-rudimentary knowledge of the failure physics of NAND flash. Program disturb, in particular, is something
by jwise0 11y ago
This is a great post, and really enhances my otherwise-rudimentary knowledge of the failure physics of NAND flash. Program disturb, in particular, is something that I didn't really have a good understanding of.
It looks like the author submitted this; if you're reading, I wrote an article a while ago [1] with some of my reverse-engineering of a NAND flash part, and I'd be interested to see which parts you think are on point and which parts seem totally wrong. I'm looking forward to your next article about device management!
[1] http://www.joshuawise.com/projects/ndfslave http://www.joshuawise.com/projects/ndfslave -- HN discussion: https://news.ycombinator.com/item?id=8133450 https://news.ycombinator.com/item?id=8133450
- cushychicken 11y agoHey Josh! I saw your original post, and I was fucking blown away by it - very nice work. It's been a while since I read it, but I seem to recall that you had the bulk of it right. I'm planning on writing another post after this one talking about some basic device management methods, and then work my way up to how they fit into embedded Flash filesystems. One of the things I'd like to do as part of this is write up the BCH error correction algorithm that's commonly implemented in NAND to check for bad bits - it's only slightly more complicated than the row/column parity algorithm you mentioned in your post. Very glad you liked the post, and flattered that you got something out of it. I saw on your site that you're a CMU graduate - did you happen to take any classes or do any research with Dr. Yu Cai? Never met him myself, but he's written some great papers on NAND Flash device physics that I've referred to frequently in studying NAND.